■ Integrated DMA Engine
- Four DMA Channels
- Internal Descriptor Support
- DMA function independent from transparent switch function
- 64-bit Addressing
- Pre-fetch Descriptor Mode
- Stride Mode

■ Multi-Host & Fail-Over Support
- 2 Configurable Non-Transparent ports
- Failover with Non-Transparent port
- Up to 2 upstream/Host ports with 1+1 failover to other upstream port

The PEX 8717 architecture supports packet cut-thru with a maximum latency of 138ns (x4 to x4). This, combined with large packet memory,
flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry
applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low
latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput.