■ PEX 8717 Key Features
o Standards Compliant
- PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0)
- PCI Power Management Spec, r1.2
- Microsoft Vista Compliant
- Supports Access Control Services
- Dynamic link-width control
- Dynamic SerDes speed control

■ Reliability, Availability, Serviceability
√visionPAK
√ Per Port Performance Monitoring
√ SerDes Eye Capture
√ PCIe Packet Generator
√ Error Injection and Loopback
- 3 Hot Plug Ports with native HP Signals
- All ports hot plug capable thru I2C
- SSC Isolation on up to 4 ports
- ECRC and Poison bit support
- Data Path parity
- Memory (RAM) Error Correction
- Advanced Error Reporting
- Port Status bits and GPIO available
- JTAG AC/DC boundary scan

The ExpressLane™ PEX8717 is a 16-lane, 10-port, PCIe Gen3 switch device developed using 40nm process node. PEX8717 offers PCI Express switching capability that enables users to create up to 9 downstream ports with varying widths including native x2. Today's processor south bridges offer x1 or x4 PCIe lanes, where x1 often does not provide enough bandwidth and x4's sheer size could waste valuable PCIe lanes. The introduction of a PLX native PCIe x2 interface, allows for optimal- or matching-bandwidth needed for new SATA, USB and SSD endpoints. Due to their backwards compatibility, designing with PCIe Gen3 switches in mixed (Gen1, Gen2 and Gen3) systems allows designers to future-proof their designs for full Gen3 enablement when migrating to next-generation end-points. The PEX8717 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. Included is PLX's proprietary visionPAK™ debug software, which allows, for example, internal receive-eye observation after equalization and access to the devices' internal debug registers thus enabling faster time to market.