RF Data Converter Subsystem
Zynq UltraScale+ RFSoCs contain an RF data converter subsystem consisting of multiple RF-ADCs and RF-DACs.

RF-ADCs
The RF-ADCs can be configured individually for real input signals. RF-ADCs in all devices other than the
XCZU43DR can also be configured as a pair for I/Q input signals. The RF-ADC tile has one PLL and a
clocking instance. Decimation filters in the RF-ADCs can operate in varying decimation modes at 80% of
Nyquist bandwidth with 89dB stop-band attenuation. Each RF-ADC contains a 48-bit numerically
controlled oscillator (NCO) and a dedicated high-speed, high-performance, differential input buffer with
on-chip calibrated 100 termination.

RF-DACs
The RF-DACs can be configured individually for real outputs. RF-DACs in all devices other than the
XCZU43DR can also be configured as a pair for I/Q output signal generation. The RF-DAC tile has one PLL
and a clocking instance. Interpolation filters in the RF-DACs can operate in varying interpolation modes at
80% of Nyquist bandwidth with 89dB stop-band attenuation. Each RF-DAC contains a 48-bit NCO.