• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range

• 25 x 18 two’s complement multiplication
• Optional pipeline stages for enhanced performance
• Optional 48-bit accumulator for multiply accumulate (MACC) operation with optional accumulator cascade to 96-bits
• Integrated adder for complex-multiply or multiply-add operation
• Optional bitwise logical operation modes
• Independent C registers per slice
• Fully cascadable in a DSP column without external routing resources
• On-Chip temperature measurement (±4°C)
• On-Chip power supply measurement (±1%)
• Easy to use, self-contained
− No design required for basic operation
− Autonomous monitoring of all on-chip sensors
− User programmable alarm thresholds for on-chip