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XC6VSX315T-L1FFG1759I 720 I/O 1600MHz IC FPGA

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XC6VSX315T-L1FFG1759I 720 I/O 1600MHz IC FPGA

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Brand Name :	Xilinx Inc.
Model Number :	XC6VSX315T-L1FFG1759I
Certification :	Lead free / RoHS Compliant
Price :	USD 7000~8500 pcs
Payment Terms :	T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :	108 pcs
Delivery Time :	3-5 Day

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XC6VSX315T-L1FFG1759I 720 I/O 1600MHz IC FPGA

XC6VSX315T-L1FFG1759I IC FPGA FCBGA-1759 Virtex-6 720 I/O

Product Attribute	Attribute Value
Manufacturer:	Xilinx
Product Category:	FPGA - Field Programmable Gate Array
Product:	Virtex-6
Number of Logic Elements:	314880
Number of I/Os:	720 I/O
Operating Supply Voltage:	1 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 100 C
Mounting Style:	SMD/SMT
Package / Case:	FCBGA-1759
Data Rate:	6.6 Gb/s
Series:	XC6VSX315T
Brand:	Xilinx
Distributed RAM:	5090 kbit
Embedded Block RAM - EBR:	25344 kbit
Maximum Operating Frequency:	1600 MHz
Moisture Sensitive:	Yes
Number of Transceivers:	24 Transceiver
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	1
Subcategory:	Programmable Logic ICs
Tradename:	Virtex

Summary of Virtex-6 FPGA Features

• Three sub-families:
• Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity
• Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity
• Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity
• Compatibility across sub-families
• LXT and SXT devices are footprint compatible in the same package
• Advanced, high-performance FPGA Logic
• Real 6-input look-up table (LUT) technology
• Dual LUT5 (5-input LUT) option
• LUT/dual flip-flop pair for applications requiring rich register mix
• Improved routing efficiency
• 64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT
• SRL32/dual SRL16 with registered outputs option
• Powerful mixed-mode clock managers (MMCM)
• MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division
• 36-Kb block RAM/FIFOs
• Dual-port RAM blocks
• Programmable
- Dual-port widths up to 36 bits
- Simple dual-port widths up to 72 bits
• Enhanced programmable FIFO logic
• Built-in optional error-correction circuitry
• Optionally use each block as two independent 18 Kb blocks

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