The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface),
tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry,
and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible.
Virtex-4 devices are produced on astate-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• True differential termination
• Selected low-capacitance I/Os for improved signal integrity
• Same edge capture at input and output I/Os
• Memory interface support for DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.