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XC5VFX30T-2FFG665I 360 I/O 550MHz Xilinx Virtex 5 FPGA

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XC5VFX30T-2FFG665I 360 I/O 550MHz Xilinx Virtex 5 FPGA

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Brand Name :	Xilinx Inc.
Model Number :	XC5VFX30T-2FFG665I
Certification :	Lead free / RoHS Compliant
Price :	USD 1000~2000 pcs
Payment Terms :	T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :	186 pcs
Delivery Time :	3-5 Day

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XC5VFX30T-2FFG665I 360 I/O 550MHz Xilinx Virtex 5 FPGA

XC5VFX30T-2FFG665I IC FPGA FBGA-665 360 I/O 550 MHz Virtex-5

Product Attribute	Attribute Value
Manufacturer:	Xilinx
Product Category:	FPGA - Field Programmable Gate Array
Product:	Virtex-5
Number of I/Os:	360 I/O
Operating Supply Voltage:	1 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 100 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-665
Data Rate:	6.5 Gb/s
Series:	XC5VFX30T
Brand:	Xilinx
Distributed RAM:	380 kbit
Embedded Block RAM - EBR:	2448 kbit
Maximum Operating Frequency:	550 MHz
Moisture Sensitive:	Yes
Number of Transceivers:	8 Transceiver
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	1
Subcategory:	Programmable Logic ICs
Tradename:	Virtex

Summary of Virtex-5 FPGA Features

• Advanced DSP48E slices
− 25 x 18, two’s complement, multiplication
− Optional adder, subtracter, and accumulator
− Optional pipelining
− Optional bitwise logical functionality
− Dedicated cascade connections

• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability

• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities

• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers

The function generators are configurable as 6-input LUTs or dual-output 5-input LUTs. SLICEMs in some CLBs can be
configured to operate as 32-bit shift registers (or 16-bit x 2 shift registers) or as 64-bit distributed RAM. In addition, the
four storage elements can be configured as either edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources.

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