• On average, one to two speed grade improvement over Virtex-4 devices
• Cascadable 32-bit variable shift registers or 64-bit distributed memory capability
• Superior routing architecture with enhanced diagonal routing supports block-to-block connectivity with minimal hops
• Up to 330,000 logic cells including:
− Up to 207,360 internal fabric flip-flops with clock enable (XC5VLX330)
− Up to 207,360 real 6-input look-up tables (LUTs) with greater than 13 million total LUT bits
− Two outputs for dual 5-LUT mode gives enhanced utilization
− Logic expanding multiplexers and I/O registers

• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities

• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers

• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
− LXT and SXT Platforms

• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
− TXT and FXT Platforms

• 65-nm copper CMOS process technology
• 1.0V core voltage
• High signal-integrity flip-chip packaging available in standard or Pb-free package options
• RocketIO GTX transceivers