Home > IC FPGA >

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

Product Categories

IC FPGA [50]
Xilinx FPGA Chip [20]
ALTERA FPGA Chip [20]
Broadcom Chip [11]
Field Programmable Gate Array [19]
Industrial Electronic Components [10]
Multilayer Ceramic Capacitor [10]
Murata Ceramic Capacitors [10]
Thin Film Resistor [10]
Isolated DC DC Converter [10]
Operational Amplifier Chip [19]
Digital Temperature Sensors [5]
RECOM DC DC Converter [10]
TRACO Power Distributors [6]

CHUANGXINDA ELECTRONICS-TECH CO., LIMITED

Contact Now

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

Ask Lasest Price
Brand Name :	Xilinx Inc.
Model Number :	XC4VLX25-11SFG363I
Certification :	Lead free / RoHS Compliant
Price :	USD 400~1000 pcs
Payment Terms :	T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :	382 pcs
Delivery Time :	3-5 Day

Add to Cart

Product Details
Company Profile

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

XC4VLX25-11SFG363I IC FPGA FBGA-363 240 I/O Virtex-4

Product Attribute	Attribute Value
Manufacturer:	Xilinx
Product Category:	FPGA - Field Programmable Gate Array
Product:	Virtex-4
Number of Logic Elements:	24192
Number of I/Os:	240 I/O
Operating Supply Voltage:	1.2 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 100 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-363
Series:	XC4VLX25
Brand:	Xilinx
Distributed RAM:	168 kbit
Embedded Block RAM - EBR:	1296 kbit
Maximum Operating Frequency:	500 MHz
Moisture Sensitive:	Yes
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	1
Subcategory:	Programmable Logic ICs
Tradename:	Virtex
Unit Weight:	5.500445 oz

Summary of Virtex-4 FPGA Features

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• 1.2V Core Voltage

• Flip-Chip Packaging including Pb-Free Package Choices

• Programmable single-ended or differential (LVDS) operation
• Input block with an optional single data rate (SDR) or double data rate (DDR) register
• Output block with an optional SDR or DDR register
• Bidirectional block
• Per-bit deskew circuitry
• Dedicated I/O and regional clocking resources
• Built in data serializer/deserializer

The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.
IOBs support the following single-ended standards:
• LVTTL
• LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI (33 and 66 MHz)
• PCI-X
• GTL and GTLP
• HSTL 1.5V and 1.8V (Class I, II, III, and IV)
• SSTL 1.8V and 2.5V (Class I and II)

Product Tags:


*From:	Your email address is incorrect!
*To:	CHUANGXINDA ELECTRONICS-TECH CO., LIMITED
*Subject:	Subject is empty!
*Message:	For the best results, we recommend including the following details: -Self introduction -Required specifications -Inquire about price/MOQ Characters Remaining: (0/3000) Please enter 20 to 3000 characters to contact this supplier!